Re: HAKMEM (well, the pieces I have anyway)
- Subject: Re: HAKMEM (well, the pieces I have anyway)
- From: mrc@Tomobiki-Cho.CAC.Washington.EDU (Mark Crispin)
- Date: 12 Sep 90 22:37:36 GMT
- Newsgroups: alt.folklore.computers
- Organization: Mendou Zaibatsu, Tomobiki-Cho, Butsumetsu-Shi
- References: <18495@ucsd.Edu> <90253.173631KPURCELL@LIVERPOOL.AC.UK>
In article <90253.173631KPURCELL@LIVERPOOL.AC.UK> KPURCELL@LIVERPOOL.AC.UK writes:
>Does anybody have a concise explanation of:
>1. PDP 6 architecture and assembley code mnemonics.
>2. PDP 10 architecture and assembley code mnemonics.
>so that I can appreciate the finer parts of HAKMEM?
The PDP-6 is the first model of PDP-10. Only a couple of dozen were
built. There were four models of PDP-10 built by DEC and a few clones
built by other vendors. Excluding the I/O instructions (which varied
from CPU to CPU and were only for the kernel), the instruction format
was a 9-bit opcode, a 4-bit field usually identifying a register
(called an "accumulator"), a 1-bit "I" indirect flag, a 4-bit "X"
index register field (accumulator 0 was never an index register, so 0
in this field meant no addressing), and an 18-bit "Y" field that was
usually either an immediate or a memory reference. This was commonly
written in assembler as one of
opcode ac,Y ; simple case
opcode ac,@Y ; indirect
opcode ac,Y(X) ; indexed
opcode ac,@Y(X) ; indexed indirect
The first thing done, even before opcode-decoding, was to calculate
the "effective address". This was done by adding the "Y" field to the
contents of the index register (if "X" non-zero) to produce an 18-bit
sum "E". If "I" is zero, E is the effective address, else the
effective address calculation was restarted on the low order 23-bits
(that is, another I,X,Y set) of the memory location addressed by E (so
you could have indirect chains).
The PDP-10 had many instructions and gonzo symmetry (there were
several cases of no-ops or equivalent instructions). Here's a bit to
give you the feel. Capitals indicate characters used in the mnemonic,
e.g. MOVNS 1,100 fetches the contents of location 100, negates it, and
puts the result back in 100 (Self) and in AC 1.
;; Comparison - 16 opcodes
Compare Accumulator [Immediate | Memory]
and skip [ | Less | Equal | LE | Always | GE | Not equal | G]
;; Conditional jump/skip - 48 opcodes
[JUMP | SKIP | Add One and Jump | Add One and Skip | Subtract One and Jump |
Subtract One and Skip] [ | Less | Equal | LE | Always | GE | Not equal | G]
;; Fixed point - 24 opcodes (IMUL/IDIV produced single-word results)
[ADD | SUB | MUL | DIV | IMUL | IDIV] [ | Immediate | to Memory | Both]
[DADD | DSUB | DMUL | DDIV]
;; also 55 floating point opcodes, FAD, DFAD, G-float, etc.
;; Single word data transmission - 16 opcodes
MOV[E | Swapped | Negative | Magnitude] [ | Immediate | to Memory | Self]
;; also an EXCHange ac/memory, BLock Transfer (the original BLT!),
;; and double-word data transmission
;; Halfword data transmission - 64 opcodes
Halfword [Right | Left] [Right | Left] [ | Zeros | Ones | Extend]
[ | Immediate | to Memory | Self]
;; Logic - 64 opcodes
[SETZero | SETOnes | SETAccumulator | SETMemory | SETComplementAccumulator |
SETComplementMemory | AND | ANDComplementAccumulator | ANDComplementMemory |
ANDComplementBoth | IOR | ORComplementAccumulator | ORComplementMemory |
ORComplementBoth | XOR | EQiValence ] [ | Immediate | Memory | Both]
;; Bitwise test - 64 opcodes
Test [Left | Right | Direct memory | Swapped memory]
[No mod | Zero | One | Complement]
and skip [ | Always | Nonzero | Equal to zero]
;; Shifts - 6 instructions
[Arithmetic SHift | ROTate | Logical SHift] [ | Combined (doubleword)]
;; "Do-loop" - 2 opcodes
Add One to Both halfwords and Jump if result [Negative | Positive]
;; Program control
XCT (execute instruction in effective address)
JFFO (non-zero bit search in AC, jump if non-zero)
JFCL (jump if math flag and clear)
JRST (jump and restore, AC field had flags for this instruction. JRST with
no flags was the fastest absolute jump. Most JRST flags were for
the kernel only)
JSR (jump to effective address+1, store return PC in effective address)
JSP (jump to effective access, store return PC in AC)
JSA/JRA (combination of worst of JSR and JSP, long obsolete)
PUSH on stack
POP from stack
PUSH pc on stack and Jump \ most common
POP from stack and Jump / subroutine call/return
ADJust Stack Pointer
;; Variable-length byte instructions
Increment Byte Pointer
ADJust Byte Pointer
[ | Increment and] [LoaD Byte | DePosit Byte]
I omitted I/O instructions and a few esoteric instructions from
this list. One instruction, EXTEND, decoded another instruction
from the effective address for a whole mess of these. Certain
opcodes were reserved for calls to the kernel, and others were
reserved for user program traps.
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